The present invention generally relates to semiconductor integrated circuits, and more particularly to a bipolar semiconductor integrated circuit having an interconnection with improved design flexibility and to a method of production of same.
The integration density of semiconductor integrated circuits is rapidly increasing due to the progress of various lithography and related techniques. Hence, the number of signal interconnections within the integrated circuit is increasing, and the size of a region for providing power source interconnections for supplying power source voltages also is increasing because of the increase in the power consumption of the integrated circuit. Especially in the case of a bipolar integrated circuit, it is impossible to reduce the current consumption of each circuit below a predetermined value which is required to maintain the high-speed operation of each of the circuits.
In addition, the number of multi-level interconnections is limited to approximately three because problems, such as disconnection or inconsistent thickness of the interconnection, are easily caused when four or more levels of interconnections are stacked. Consequently, the chip size becomes large because of the need to increase the number of signal interconnections in each level and to widen the power source interconnections. Hence, there is a demand to prevent such an increase of the chip size. On the other hand, when the length of the signal interconnection is long, it is impossible to achieve high-speed circuit operation even when high-speed circuit elements are used.
FIGS. 1A and 1B are a plan view and a cross sectional view, respectively, showing an example of a conventional semiconductor integrated circuit. In FIGS. 1A and 1B, a semiconductor chip 12 is accommodated within a stage 11 of a package 10. Terminals 13 for signal input and output and terminals 14 for supplying power source voltages V.sub.CC and V.sub.EE are provided on the semiconductor chip 12, and these terminals 13 and 14 are wire-bonded to package leads 15.
A first power source interconnection (not shown) for the power source voltage V.sub.CC and a second power source interconnection 16 for the power source voltage V.sub.EE are provided on the semiconductor chip 12. The first and second power source interconnections respectively have stripe patterns and are oriented relatively to each other such that the first, if shown in FIG. 1A, would intersect the second in the plan view. In use, and for example, an emitter coupled logic (ECL) circuit may be formed between the first and second power source interconnections.
FIG. 2 is a cross sectional view of the semiconductor chip 12. As shown in FIG. 2, the semiconductor chip 12 has a p.sup.- -type substrate 21 provided with a metallized layer 20 on a back surface thereof. An n.sup.+ -type buried layer 22 which becomes a collector, an n-type epitaxial layer 23, a p.sup.+ -type isolation layer 24, a p-type diffusion layer 25 which becomes a base, an n.sup.+ -type diffusion layer 26 which becomes an emitter, an n.sup.+ -type diffusion layer 27 which becomes a collector contact, and a p-type diffusion layer 28 which becomes a resistor, are provided on a front surface (i.e., the upper, main surface, as shown in FIG. 2) of the p.sup.- -type substrate 21. In addition, the semiconductor chip 12 has insulator layers 29 and 30 indicated by cross-hatching, a first interconnection 31, and a second interconnection 32. For example, the second interconnection 32 corresponds to the second power source interconnection 16 for the power source voltage V.sub.EE shown in FIGS. 1A and 1B.
When considering an integrated circuit with 1,000 gates where the current consumption is 1 mA per gate, for example, a current of 1A flows in total. When the power source interconnection is an aluminum interconnection having a current density of 2.times.10.sup.5 A/cm.sup.2 and a thickness of 1 micron, the power source interconnection needs a large width of 0.5 mm. In addition, there are problems in that a voltage drop caused by the large current flow is large in the power source interconnection having the stripe pattern and that the noise margin of the circuit is poor.
Because of the need to reduce the capacitance between the collector (region 22) and the substrate 21, that is, mainly the capacitance introduced between the n.sup.+ -type buried layer 22 and the substrate 21, the substrate 21 has a low impurity density with a high resistivity in the range of 5 .OMEGA.cm to 30 .OMEGA.cm. Normally, the substrate 21 has a thickness of 500 microns, and for this reason, it is impossible to supply the power source voltage from the back surface of the substrate 21 when the voltage drop is taken into account. Thus, the first and second interconnections 31 and 32 are used to supply the power source voltages.
Therefore, the conventional semiconductor integrated circuit suffers problems in that the voltage drop is large due to the long power source interconnections, and the freedom with which the signal interconnections may be designed is limited because the signal interconnections must be positioned so as to avoid the power source interconnections. In other words, the design flexibility of the interconnection is poor in the conventional integrated circuit. Furthermore, there is another problem in that the chip size becomes large because of the need to provide a large number of terminals for the power source voltages on the semiconductor chip.
In order to overcome the problem, a coinventor herein proposed a semiconductor integrated circuit shown in the Japanese Laid-open Patent Application No. 01-73669 published on Mar. 17, 1989 and corresponding to the United States patent application Ser. No. 243,745 filed Sep. 13, 1988, European Patent Application No. 88114886.0 filed Sep. 12, 1988 and Korean Patent Application No. 88-11860 filed Sep. 14, 1988, the construction of which is shown in FIG. 3. The inventor of the aforesaid U.S. and corresponding foreign applications, each thereof assigned to Fujitsu Limited, is Masayuki Kokado, a coinventor of the present application.
Referring to FIG. 3, the proposed device has a p.sup.+ -type substrate 41 having a high impurity density with a resistivity of 0.1 .OMEGA.cm or less. A metallized layer (conductive layer) 42 is provided on a back (or lower, main) surface of the p.sup.+ -type substrate 41. A p.sup.- -type epitaxial layer (first p-type layer) 43 having a high resistivity in the range of 1 .OMEGA.cm to 30 .OMEGA.cm is formed on a front (or upper, main) surface of the p.sup.+ -type substrate 41. A p.sup.+ -type layer (second p-type layer) or region 44 having a low resistivity is formed in a selected position within the p.sup.- -type epitaxial layer 43.
Similarly as in the case of the conventional semiconductor chip shown in FIG. 2 described before, an n.sup.+ -type buried layer 22a which becomes a collector, an n-type epitaxial layer 23a, a p.sup.+ -type isolation layer or region 24a, a p-type diffusion layer 25a which becomes a base, an n.sup.+ -type diffusion layer 26a which becomes an emitter, an n.sup.+ -type diffusion layer 27a which becomes a collector contact, and a p-type diffusion layer 28a which becomes a resistor are provided on the front (upper, main) surface of the p.sup.+ -type substrate 41. In addition, the semiconductor chip has insulator layers 29a and 30a indicated by cross-hatching, a first interconnection 31a, and a second interconnection 32a.
Hence, a conductor path is formed from the metallized layer 42 to the first and second interconnections 31a and 32a through the p.sup.+ -type substrate 41 having the low resistivity, the p.sup.+ -type layer 44 and the p.sup.+ -type isolation layer 24a. The second interconnection 32a is connected to transistors and resistor elements formed on the front substrate (or top) surface of the substrate 41.
According to the semiconductor integrated circuit of this previous proposal, the length of the power source interconnection is shortened and the voltage drop can be decreased compared to the conventional semiconductor integrated circuit. In addition, the noise margin is improved and it is possible to achieve high-speed circuit operation. Moreover, because the conductor path for supplying the power source voltage is arranged vertically on the substrate, the signal interconnections can be designed with a large degree of freedom, thereby making it possible to prevent the chip size from increasing.
In this previous semiconductor integrated circuit, however, there arises a problem in that the voltage which may be applied to the substrate 41 via the metallized layer 42 is limited to a low voltage. Note that there is formed a p-n junction in this structure, as shown by shading in FIG. 3 between the region 24a and the layer 23a, which permits the current to leak into the layer 232 and further to the layer 27a through the p-n junction when the voltage applied to the metallized layer 42 exceeds the threshold voltage of the p-n junction. Such a forward biasing of the p-n junction can occur when the voltage at the epitaxial layer 23a becomes lower than the voltage at the p.sup.+ -type isolation layer 24a in response, for example, to the collector voltage appearing in the collector contact region 27a. Thus, in order to avoid the undesirable forward biasing of the p-n junction, it is necessary to maintain the voltage at the layer 24a, and hence the voltage applied to the metallized layer 42, as low as possible. As a matter of fact, the voltage which may be applied to the metallized layer 42 is limited to the most negative voltage used in the integrated circuit.
A similar problem occurs also in the case that the conductive type of the semiconductor layers in FIG. 3 is reversed. In this case, the voltage which may be applied to the metallized layer 42 is limited to the most positive voltage used in the integrated circuit. Hence, the integrated circuit of FIG. 3 has a problem in that the degree of freedom of circuit design is substantially limited.